Analysis and design of wideband voltage controlled oscillators using self-oscillating active inductors.

Voltage controlled oscillators (VCOs) are essential components of RF circuits used in transmitters and receivers as sources of carrier waves with variable frequencies. This, together with a rapid development of microelectronic circuits, led to an extensive research on integrated implementations of the oscillator circuits. One of the known approaches to oscillator design employs resonators with active inductors electronic circuits simulating the behavior of passive inductors using only transistors and capacitors. Such resonators occupy only a fraction of the silicon area necessary for a passive inductor, and thus allow to use chip area more eectively. The downsides of the active inductor approach include: power consumption and noise introduced by transistors. This thesis presents a new approach to active inductor oscillator design using selfoscillating active inductor circuits. The instability necessary to start oscillations is provided by the use of a passive RC network rather than a power consuming external circuit employed in the standard oscillator approach. As a result, total power consumption of the oscillator is improved. Although, some of the active inductors with RC circuits has been reported in the literature, there has been no attempt to utilise this technique in wideband voltage controlled oscillator design. For this reason, the dissertation presents a thorough investigation of self-oscillating active inductor circuits, providing a new set of design rules and related trade-os. This includes: a complete small signal model of the oscillator, sensitivity analysis, large signal behavior of the circuit and phase noise model. The presented theory is conrmed by extensive simulations of wideband CMOS VCO circuit for various temperatures and process variations. The obtained results prove that active inductor oscillator performance is obtained without the use of standard active compensation circuits. Finally, the concept of self-oscillating active inductor has been employed to simple and fast OOK (On-Off Keying) transmitter showing energy eciency comparable to the state of the art implementations reported in the literature

Analysis and design of oscillators based on low-voltage self-oscillating active inductors

This paper presents a new consistent analysis of self-oscillating active in- ductors together with a complete design example of a 90 nm CMOS current controlled oscillator (CCO) for ISMapplications. Using the proposed passive compensation method in place of a standard negative impedance converter, typical performance of active induc- tor oscillator is achieved with reduced static power consumption. The article presents a small signal, large signal and phase noise analysis of the proposed oscillator together with related design trade-offs. Theoretical results are confirmed by a simulation of cur- rent controlled oscillator designed using UMC 90 nm 1P9M RF process libraries. The proposed circuit achieves a relative tuning range of 26% with a 434 MHz carrier fre- quency and average in band phase noise of -92 dBc/Hz at 1 MHz offset. The maximum power consumption of the oscillator core is only 2 mW from a 1 V supply

Negative resistance generation in degenerated gyrator

In this paper the concept of a degenerated gyrator is presented. Using the proposed method, a negative resistance can be generated in a gyrator circuit using only passive components. Simulation results show that the negative resistance produced by gyrator degeneration allows stable harmonic oscillations to be obtained in an active inductor circuit without the use of any additional components

350 mV, 0.5 mW, 5 GHz, 130 nm CMOS Class-C VCO Design Using Open Loop Analysis

This paper presents a design method of LC cross-coupled oscillators using a large signal S-parameter open loop approach instead of typical negative resistance methodology presented in the liter- ature. The open loop technique allows extraction of loaded quality factor of the complete oscillator circuit and observe how oscillation conditions change with increasing oscillator signal amplitude. As a result, highly non-linear modes of oscillator operation (class-C in this case), can be analysed without necessity of conducting time consuming transient simulations. The presented method is not technology specific and allows fast calculations under changing bias conditions. The simulated class-C 130 nm CMOS oscillator operates at 5 GHz from a reduced power supply of 350 mV, achieving average SSB phase noise better than -115 dBc/Hz at 1 MHz offset from the carrier, using a relatively low loaded quality factor (QL ≈ 10) LC resonator. The presented VCO has tuning range of 280 MHz to compensate for process and temperature variations. In steady state, MOSFET devices in the oscillator operate in class-C i.e. for VGS <Vth, resulting in low power consumption of less than 0.5 mW RMS

Linearity vs. Power Consumption of CMOS LNAs in LTE Systems

This paper presents a study of linearity in wideband CMOS low noise amplifiers (LNA) and its relationship to power consumption in context of Long Term Evolution (LTE) system. Using proposed figure of merit to compare 35 state-of-the-art LNA circuits published in recent years, the paper shows a proportional but relatively weak dependence between amplifier performance (that is combined linearity, noise figure and gain) with power consumption. As a result, the predicted increase of LNA performance, necessary to satisfy stringent linearity specifications of LTE standard, may require a significant increase in power, a critical budget planning aspect for both handheld devices and base stations operating in small cells

350 mV, 0.5 mW, 5 GHz, 130 nm CMOS Class-C VCO Design Using Open Loop Analysis

This paper presents a design method of LC cross-coupled oscillators using a large signal S-parameter open loop approach instead of typical negative resistance methodology presented in the liter- ature. The open loop technique allows extraction of loaded quality factor of the complete oscillator circuit and observe how oscillation conditions change with increasing oscillator signal amplitude. As a result, highly non-linear modes of oscillator operation (class-C in this case), can be analysed without necessity of conducting time consuming transient simulations. The presented method is not technology specific and allows fast calculations under changing bias conditions. The simulated class-C 130 nm CMOS oscillator operates at 5 GHz from a reduced power supply of 350 mV, achieving average SSB phase noise better than -115 dBc/Hz at 1 MHz offset from the carrier, using a relatively low loaded quality factor (QL ≈ 10) LC resonator. The presented VCO has tuning range of 280 MHz to compensate for process and temperature variations. In steady state, MOSFET devices in the oscillator operate in class-C i.e. for VGS <Vth, resulting in low power consumption of less than 0.5 mW RMS

10 GHz, Class-B, 0.5 V, 130 nm CMOS Cross-Coupled Oscillator Design Using Open-Loop Technique

The paper presents a method for design of LC cross-coupled oscillators based on open-loop technique and its practical application leading to a high frequency CMOS oscillator prototype. Thanks to the proposed approach, main circuit parameters as loaded quality factor (responsible for phase noise performance of LC oscillator) and steady-state oscillation amplitude can be extracted, without the necessity of time consuming transient simulations. The presented method is not technology specific and allows fast calculations under changing bias conditions. The proposed 130 nm CMOS prototype operates 10 GHz from 0.5 V power supply achieving SSB phase noise of -113 dBc/Hz at 1 MHz offset from the carrier. Low power consumption of 1.09 mW RMS, has been obtained by biasing the oscillator devices to operate in class-B i.e. VGS =Vth

Using large signal S-parameters to design low power class-B and class-C CMOS cross-coupled voltage controlled oscillators.

This article presents a method for design of cross-coupled LC oscillators using open-loop technique and large signal scattering matrix parameters (S-parameters) in place of well known and established negative resistance approach. Thanks to the open-loop methodology, the main circuit parameters such as loaded quality factor, steady-state oscillation amplitude and signal frequency under large signal regime can be extracted without, often tedious and time consuming, transient simulations. The most important aspect of the proposed method is its ability to provide relatively simple and intuitive representation of a cross-coupled oscillator under changing bias conditions, with 10% accuracy in comparison to analysis in time domain. The presented methodology is not technology specific, however CMOS was chosen due to its availability, relative low cost and popularity of circuit implementation. The article shows two low power, sub-1 V voltage controlled oscillator prototypes, one operating in class-B, the other one in class-C, designed using the described method and operating under the reduced power supply requirements yet retaining a state of the art Figure of Merit (FoM) of various VCO reported in the literature

Wideband Tx Leakage Cancellation using Adaptive Delay Filter at RF Frequencies

Transmitter leakage is caused by limited isolation between Tx and Rx paths of an frequency-division duplexing (FDD) transceiver due to use of non-ideal duplexers. As the leakage can seriously impair the performance of the receiver, it is important to increase the isolation of the existing system. A portion of the leakage falling into the Rx band can't be removed using conventional band-pass techniques, which leads to exploration of active cancellation methods. This paper presents an active Tx leakage cancellation structure with adaptive delay filter, together with a related design method- ology. Based on S-parameters characterisation of a SAW duplexer, simulation results show that for 20 MHz bandwidth more than 25 dB cancellation can be achieved, for LTE band 8 carrier. The complexity of proposed cancellation structure is proportional to the characteristics of a duplexer used in the transceiver. Using finite number of elements, the number of auxiliary paths needed depends on how complex the characteristics of the duplexer are within the band of interest

Wide Band Switched Delay Line using MEMS Switches

This paper presents a high precision wide band switched delay line with fine tuning capability and low insertion loss. The circuit is designed to operate in the frequency range from 1 GHz to 5 GHz and tuned using MEMS switches targeting a minimum delay step of 7 ps. The delay line uses a single layer of a high permittivity substrate ("r =10), and the MEMS devices are interconnected using conventional coplanar waveguide technology (CPW). The circuit was designed and simulated using CST Microwave Studio. The simulated group delay shows a small deviation from the linear phase of less than 1o over a wide bandwidth compared to the performance of SAW and ceramic filters [1]. The simulation results shows an insertion loss and a return loss of better than 1 dB and 20 dB respectively